1. Field of Invention
The present invention relates to the arrangement of conductive pads on a package and the corresponding pads on a circuit board, especially to the arrangement of conductive pads on a grid array package and the corresponding pads on a circuit board.
2. Related Art
Typically, semiconductor chip is disposed on a package to electrically connect with a circuit board. The package provides the well protections against the chemistry, moisture, static-electric damage and other damages to prolong the lifetime of the chip. One common type of the packages is a ball grid array (BGA) package. A conventional grid array package 100 has a substrate 101, a chip 102 disposed on the substrate 101, a plurality of conductive wires 103 and a molding material 104. As shown in FIG. 1a, the package 100 is for example a BGA package using wire-bonding technology. The substrate 101 and the chip 102 are electrically connected through the conductive wires 103, and then the molding material 104 encapsulates the chip 102 and the conductive wires 103 for the well-protections. The package 100 further has a plurality of solder balls 105 disposed on a surface of the substrate 101 for the electrical connections with a circuit board 120.
Referring to FIG. 1b, the solder balls 105 are regularly disposed in rows and columns. One row of the solder balls 105 is apart from the adjacent row of the solder balls 105 at a pitch S0. Similarly, one column of the solder balls is apart from the adjacent column at the same pitch S0. Thus, the solder balls 105 disposed in the rows and columns are like a ball grid array on the bottom surface of the package 100. There are a plurality of virtual grids in the crossings of the rows and the columns, and the solder balls 105 are disposed on the virtual grids. The solders balls 105 are disposed in the pitch S0.
The grid array packages similar to the BGA package include, for example pin grid array (PGA) package and land grid array (LGA) package. Although these electrical connections between the package 100 and the circuit board 120 are different, all of the electrical connections are arranged in an array of rows and columns. Therefore, the solder balls 105 disposed on the package 100 and the conductive pads 125 disposed on the circuit board 120 are populated at the crossings of the rows and columns. However, BGA packages are widely used in current IC packaging industry because of the advantages of BGA packages, such as high reliability, good thermal and electrical performance, and mature manufacture process.
The solder balls 105 of the BGA package are used as the electric contacts with a circuit board 120. More particularly, one solder ball 105 is in contact with one conductive pad 125 disposed on the circuit board 120. In the other words, the arrangement of the solder balls 105 is the one-on-one mapping of the arrangement of the conductive pads 125. FIG. 1c shows the conventional arrangement of the conductive pads 125 on the circuit board 120 to connect with the grid array package 100. A plurality of conductive pads 125 respectively corresponding to the solder balls 105 of the package 100 dispose on a surface of the circuit board 120. Furthermore, the conductive pads 125 are electrically connected to other components disposed in the circuit board 120, such as the power/ground plane, the decoupling capacitor or other devices. Each conductive pad 125 disposed in the peripheral region is connected with a conductive trace 121 on the surface of the circuit board 120. The conductive trace 121 is extending toward the outer region on the circuit board 120 which is not under the package 100. Because of the limitation in the pitch S0 of two adjacent conductive pads 125, one conductive pad 125 disposed in the inner region of the conductive pads are electrically connected to the internal circuit of the circuit board 120 via a conductive trace 122 and a through hole 126 nearby.
The grid array package provides a high amount of contacts for the package and the circuit board comparing with the other package, such as the Quad Flat No-Lead (QFN) Package. As more functions are being integrated in the semiconductor chip, it is necessary to provide more contacts between the package and the circuit board. However, the available surface on a chip is shrunk as the development of the manufacturing process and the thirst for high performance. The arrangement of the conductive pads and the traces routing are more and more complex and difficult. It is thus imperative to provide a denser contacts in the same dimension for the grid array package is a serious challenge for the designers of circuit board and package.